Memory devices typically contain a large number of memory cells arranged in rows and columns. Although memory cells and other circuitry in memory devices are normally very reliable, the large number of memory cells in memory devices may result in a significant probability that there will be at least one defective memory cell in every memory device. To avoid the need to discard such memory devices as defective, techniques have been developed to repair memory cells, particularly as long as relatively few memory cells are defective. Memory cells are typically repaired on a row-by-row or a column-by-column basis in which a redundant row or column may be substituted for a row or column, respectively, containing one or more defective memory cells. The address of the defective row or column may then be recorded and compared to a row or column address associated with a received memory request (e.g., a request to write to or read from memory) to detect an access to a row or column that has been determined to include a defective memory cell (hereinafter “a defective memory cell”). The received address may then be redirected (e.g., re-mapped) to the address of the corresponding row or column of memory cells.
The above-described technique for repairing defective memory cells can be effective in salvaging memory devices as long as the number of rows or columns containing a defective memory cell does not exceed the number of redundant rows or columns provided in the memory device. However, there are usually an adequate number of redundant rows or columns as long as each defect in the memory device affects only a single row or column. A defect may make multiple rows or columns unusable if the defect occurs in a component of the memory device data path that affects multiple rows or columns. More specifically, memory cells are typically arranged in sections of memory cells, which are typically referred to, for example, as “arrays” or “blocks” and in some cases “banks.” The memory cells in each section may be arranged in rows and columns. The memory cells in each column are usually coupled to either a respective digit line for that column or a respective pair of complementary digit lines for that column. A sense amplifier may be provided for each column of memory cells, and it may be connected by the digit line(s) to the memory cells in the respective column. All of the sense amplifiers for the section of memory cells are normally connected to one or more pairs of complementary input/output (“I/O”) lines. Each pair of I/O lines may then be connected to a respective differential sense amplifier, which is sometimes also known as a “helper flip-flop.” Therefore, a defect in a complementary pair of I/O lines, such as a short circuit between the I/O lines, or a defect in one of the differential sense amplifiers, can render the entire section of memory cells defective.
The number of rows and columns of memory cells in a typical section normally far exceeds the number of redundant rows and redundant columns in a memory device. Although the number of redundant rows and columns could, of course, be vastly increased, the amount of circuitry that would be needed to support such a large number of redundant rows and columns may be immense. For example, a typical section contains 2,048 columns of memory cells and 512 rows of memory cells. In practice, 8 columns are simultaneously addressed to simultaneously provide 8 bits of data, thus necessitating only 256 (2,048/8) column decoders but requiring 8 sets (e.g., pairs) of I/O lines.
To be able to use each of these redundant rows and columns, may require circuitry, such as an array of anti-fuses, to record the address of each defective row or column. Therefore, 768 (512+256) sets of anti-fuses or other address recording devices may be required to record the addresses in order to repair all of the rows and columns in a section. Also required would be 768 circuits for comparing the recorded addresses of defective rows and columns with received addresses. Therefore, the large amount of memory cells that are unusable when a defect occurs “downstream” from a row or column of memory cells, such as in a pair of I/O lines, makes repair of such defects impractical. As a result, memory devices containing such types of defects must normally be scrapped.
There is therefore a need for a technique to allow repair of the memory cells in an entire section, such as an array or block, without requiring an excessive amount of circuitry to support such repairs.